297 lines
8.2 KiB
C++
297 lines
8.2 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include <iosfwd>
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#include <tuple>
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#include <type_traits>
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#include <vector>
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#include "Common/CommonTypes.h"
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#include "Core/Debugger/PPCDebugInterface.h"
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#include "Core/PowerPC/BreakPoints.h"
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#include "Core/PowerPC/ConditionRegister.h"
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#include "Core/PowerPC/Gekko.h"
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#include "Core/PowerPC/PPCCache.h"
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class CPUCoreBase;
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class PointerWrap;
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namespace PowerPC
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{
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// The gaps in the CPUCore numbering are from cores that only existed in the past.
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// We avoid re-numbering cores so that settings will be compatible across versions.
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enum class CPUCore
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{
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Interpreter = 0,
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JIT64 = 1,
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JITARM64 = 4,
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CachedInterpreter = 5,
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JITKVM = 6,
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};
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// For reading from and writing to our config.
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std::istream& operator>>(std::istream& is, CPUCore& core);
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std::ostream& operator<<(std::ostream& os, CPUCore core);
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enum class CoreMode
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{
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Interpreter,
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JIT,
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};
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// TLB cache
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constexpr size_t TLB_SIZE = 128;
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constexpr size_t NUM_TLBS = 2;
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constexpr size_t TLB_WAYS = 2;
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struct TLBEntry
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{
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static constexpr u32 INVALID_TAG = 0xffffffff;
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u32 tag[TLB_WAYS] = {INVALID_TAG, INVALID_TAG};
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u32 paddr[TLB_WAYS] = {};
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u32 pte[TLB_WAYS] = {};
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u8 recent = 0;
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};
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struct PairedSingle
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{
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u64 PS0AsU64() const { return ps0; }
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u64 PS1AsU64() const { return ps1; }
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u32 PS0AsU32() const { return static_cast<u32>(ps0); }
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u32 PS1AsU32() const { return static_cast<u32>(ps1); }
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double PS0AsDouble() const;
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double PS1AsDouble() const;
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void SetPS0(u64 value) { ps0 = value; }
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void SetPS0(double value);
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void SetPS1(u64 value) { ps1 = value; }
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void SetPS1(double value);
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void SetBoth(u64 lhs, u64 rhs)
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{
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SetPS0(lhs);
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SetPS1(rhs);
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}
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void SetBoth(double lhs, double rhs)
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{
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SetPS0(lhs);
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SetPS1(rhs);
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}
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void Fill(u64 value) { SetBoth(value, value); }
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void Fill(double value) { SetBoth(value, value); }
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u64 ps0 = 0;
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u64 ps1 = 0;
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};
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// Paired single must be standard layout in order for offsetof to work, which is used by the JITs
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static_assert(std::is_standard_layout<PairedSingle>(), "PairedSingle must be standard layout");
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// This contains the entire state of the emulated PowerPC "Gekko" CPU.
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struct PowerPCState
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{
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u32 gpr[32]; // General purpose registers. r1 = stack pointer.
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u32 pc; // program counter
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u32 npc;
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ConditionRegister cr;
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UReg_MSR msr; // machine state register
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UReg_FPSCR fpscr; // floating point flags/status bits
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// Exception management.
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u32 Exceptions;
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// Downcount for determining when we need to do timing
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// This isn't quite the right location for it, but it is here to accelerate the ARM JIT
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// This variable should be inside of the CoreTiming namespace if we wanted to be correct.
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int downcount;
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// XER, reformatted into byte fields for easier access.
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u8 xer_ca;
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u8 xer_so_ov; // format: (SO << 1) | OV
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// The Broadway CPU implements bits 16-23 of the XER register... even though it doesn't support
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// lscbx
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u16 xer_stringctrl;
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// gather pipe pointer for JIT access
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u8* gather_pipe_ptr;
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u8* gather_pipe_base_ptr;
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#if _M_X86_64
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// This member exists for the purpose of an assertion in x86 JitBase.cpp
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// that its offset <= 0x100. To minimize code size on x86, we want as much
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// useful stuff in the one-byte offset range as possible - which is why ps
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// is sitting down here. It currently doesn't make a difference on other
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// supported architectures.
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std::tuple<> above_fits_in_first_0x100;
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#endif
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// The paired singles are strange : PS0 is stored in the full 64 bits of each FPR
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// but ps calculations are only done in 32-bit precision, and PS1 is only 32 bits.
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// Since we want to use SIMD, SSE2 is the only viable alternative - 2x double.
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alignas(16) PairedSingle ps[32];
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u32 sr[16]; // Segment registers.
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// special purpose registers - controls quantizers, DMA, and lots of other misc extensions.
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// also for power management, but we don't care about that.
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u32 spr[1024];
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// Storage for the stack pointer of the BLR optimization.
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u8* stored_stack_pointer;
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std::array<std::array<TLBEntry, TLB_SIZE / TLB_WAYS>, NUM_TLBS> tlb;
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u32 pagetable_base;
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u32 pagetable_hashmask;
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InstructionCache iCache;
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void UpdateCR1()
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{
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cr.SetField(1, (fpscr.FX << 3) | (fpscr.FEX << 2) | (fpscr.VX << 1) | fpscr.OX);
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}
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void SetSR(u32 index, u32 value);
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};
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#if _M_X86_64
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static_assert(offsetof(PowerPC::PowerPCState, above_fits_in_first_0x100) <= 0x100,
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"top of PowerPCState too big");
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#endif
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extern PowerPCState ppcState;
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extern BreakPoints breakpoints;
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extern MemChecks memchecks;
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extern PPCDebugInterface debug_interface;
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const std::vector<CPUCore>& AvailableCPUCores();
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CPUCore DefaultCPUCore();
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void Init(CPUCore cpu_core);
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void Reset();
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void Shutdown();
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void DoState(PointerWrap& p);
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void ScheduleInvalidateCacheThreadSafe(u32 address);
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CoreMode GetMode();
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// [NOT THREADSAFE] CPU Thread or CPU::PauseAndLock or Core::State::Uninitialized
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void SetMode(CoreMode _coreType);
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const char* GetCPUName();
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// Set the current CPU Core to the given implementation until removed.
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// Remove the current injected CPU Core by passing nullptr.
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// While an external CPUCoreBase is injected, GetMode() will return CoreMode::Interpreter.
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// Init() will be called when added and Shutdown() when removed.
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// [Threadsafety: Same as SetMode(), except it cannot be called from inside the CPU
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// run loop on the CPU Thread - it doesn't make sense for a CPU to remove itself
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// while it is in State::Running]
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void InjectExternalCPUCore(CPUCoreBase* core);
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// Stepping requires the CPU Execution lock (CPU::PauseAndLock or CPU Thread)
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// It's not threadsafe otherwise.
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void SingleStep();
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void CheckExceptions();
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void CheckExternalExceptions();
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void CheckBreakPoints();
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void RunLoop();
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u64 ReadFullTimeBaseValue();
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void WriteFullTimeBaseValue(u64 value);
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void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
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// Easy register access macros.
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#define HID0 ((UReg_HID0&)PowerPC::ppcState.spr[SPR_HID0])
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#define HID2 ((UReg_HID2&)PowerPC::ppcState.spr[SPR_HID2])
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#define HID4 ((UReg_HID4&)PowerPC::ppcState.spr[SPR_HID4])
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#define DMAU (*(UReg_DMAU*)&PowerPC::ppcState.spr[SPR_DMAU])
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#define DMAL (*(UReg_DMAL*)&PowerPC::ppcState.spr[SPR_DMAL])
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#define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0])
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#define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1])
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#define PC PowerPC::ppcState.pc
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#define NPC PowerPC::ppcState.npc
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#define FPSCR PowerPC::ppcState.fpscr
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#define MSR PowerPC::ppcState.msr
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#define GPR(n) PowerPC::ppcState.gpr[n]
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#define rGPR PowerPC::ppcState.gpr
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#define rSPR(i) PowerPC::ppcState.spr[i]
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#define LR PowerPC::ppcState.spr[SPR_LR]
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#define CTR PowerPC::ppcState.spr[SPR_CTR]
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#define rDEC PowerPC::ppcState.spr[SPR_DEC]
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#define SRR0 PowerPC::ppcState.spr[SPR_SRR0]
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#define SRR1 PowerPC::ppcState.spr[SPR_SRR1]
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#define SPRG0 PowerPC::ppcState.spr[SPR_SPRG0]
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#define SPRG1 PowerPC::ppcState.spr[SPR_SPRG1]
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#define SPRG2 PowerPC::ppcState.spr[SPR_SPRG2]
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#define SPRG3 PowerPC::ppcState.spr[SPR_SPRG3]
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#define GQR(x) PowerPC::ppcState.spr[SPR_GQR0 + (x)]
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#define TL PowerPC::ppcState.spr[SPR_TL]
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#define TU PowerPC::ppcState.spr[SPR_TU]
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#define rPS(i) (PowerPC::ppcState.ps[(i)])
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inline void SetCarry(u32 ca)
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{
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PowerPC::ppcState.xer_ca = ca;
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}
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inline u32 GetCarry()
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{
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return PowerPC::ppcState.xer_ca;
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}
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inline UReg_XER GetXER()
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{
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u32 xer = 0;
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xer |= PowerPC::ppcState.xer_stringctrl;
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xer |= PowerPC::ppcState.xer_ca << XER_CA_SHIFT;
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xer |= PowerPC::ppcState.xer_so_ov << XER_OV_SHIFT;
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return UReg_XER{xer};
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}
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inline void SetXER(UReg_XER new_xer)
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{
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PowerPC::ppcState.xer_stringctrl = new_xer.BYTE_COUNT + (new_xer.BYTE_CMP << 8);
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PowerPC::ppcState.xer_ca = new_xer.CA;
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PowerPC::ppcState.xer_so_ov = (new_xer.SO << 1) + new_xer.OV;
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}
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inline u32 GetXER_SO()
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{
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return PowerPC::ppcState.xer_so_ov >> 1;
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}
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inline void SetXER_SO(bool value)
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{
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PowerPC::ppcState.xer_so_ov |= static_cast<u32>(value) << 1;
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}
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inline u32 GetXER_OV()
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{
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return PowerPC::ppcState.xer_so_ov & 1;
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}
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inline void SetXER_OV(bool value)
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{
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PowerPC::ppcState.xer_so_ov = (PowerPC::ppcState.xer_so_ov & 0xFE) | static_cast<u32>(value);
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SetXER_SO(value);
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}
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void UpdateFPRF(double dvalue);
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} // namespace PowerPC
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